1. Field of the Invention
The present invention relates to a 3D stacked NAND flash memory array, and more particularly to a 3D stacked NAND flash memory array having SSL status check buildings for monitoring threshold voltages of string selection transistors, a monitoring method of threshold voltages of string selection transistors by the SSL status check buildings, and an operating method of the 3D stacked NAND flash memory array having SSL status check buildings.
2. Description of the Related Art
Recently, the utilization of flash memories as high integrity mass storage devices has been increasing, but there has been difficulty in improving the degree of integrity under 20 nm due to limitation of the photolithography technology. Thus, various NAND flash memory arrays enabling three-dimensional (3D) stack have been studied.
When the memory structure having a 3D stacked shape is compared with the conventional two-dimensional (2D) planar structure as shown in FIG. 1, the greatest difference is a necessity of a layer selection in the 3D stacked memory structure during operation.
These days, the various 3D structures enabling a layer selection in the operation of writing (a program) and reading (a read) are being studied. One example is a 3D NAND flash memory array distinguishing stacked layers from each other by electrical erases described in Korean Publication No. 10-2011-0111166.
The prior art is known as a structure performing a layer selection by erase operation (LASER). According to this structure, each SSL (LSL shown in FIG. 1 of Korean Publication No. 10-2011-0111166 is equal to SSL) and a body of an active line separately formed by each layer are used to extract electrons from a specific charge storage layer between the SSL and the body of the active line in each layer for electrically forming an erase state combination, namely an initialized state combination, instead of the impurity-doped layer combination physically formed in the conventional Korean Patent No. 10-1036155. So, it has merits that the layer selection can be more easily performed.
However, the LASER structure is needed to have the more number of SSLs in case of the more number of layers. Considering that the general width of SSL (String Selection Line), in more details, the gate length of a string selection transistor is 4-5 times larger than that of a memory cell (i.e., the width of a word line) to overcome some problems such as a leakage current, short channel effect, etc., there has been a gradually rising necessity to maximally inhibit the increasing number of required SSLs according to the increasing number of layers.
To solve the problems of the LASER structure, a 3D stacked NAND flash memory array enabling a layer selection by multi-level operation (LSM) and an operation method thereof have been developed and filed as Korean Application No. 10-2012-0019349 by the present applicant. It is possible to get rid of the waste of unnecessary areas by minimizing an increase in the number of string selection lines (SSLs) though vertically stacked layers are increased.
By the way, in order to normally operate a layer selection by SSL, the LASER structure and the 3D stacked NAND flash memory array enabling LSM need a check on threshold voltages of string selection transistors formed with SSL. For checking the threshold voltages of string selection transistors, timing sequences may be further added between the regular operations (a program, a read and an erase).
However, if extra timing sequences are added to check the threshold voltages of string selection transistors in the 3D stacked NAND flash memory array, it restricts the NAND operations used in the conventional 2D plane structure shown in FIG. 1 and finally produces loss problems in operation speed and efficiency compared to the conventional art.